(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of eliminating defects caused by copper flaking after CMP in the manufacture of integrated circuits.
(2) Description of the Prior Art
In a common application for integrated circuit fabrication, a contact/via opening is etched through an insulating layer to an underlying conductive area to which electrical contact is to be made. A barrier layer is formed within the contact/via opening. A conducting layer material is deposited within the contact/via opening. Because of its lower bulk resistivity, Copper (Cu) metallization is the future technology for feature sizes in the deep sub-half-micron regime. Cu has been used successfully as an interconnection line. Low dielectric constant materials are preferred as the insulating layer in the copper interconnect process in order to improve RC time delay. After the copper is deposited within the opening, it is typically polished back by chemical mechanical polishing (CMP) to leave the copper only within the opening. After this CMP process, flakes of copper form on the surface of the copper and dielectric layers after a Q-time of more than 12 hours. If the copper flakes remain, metal bridging will be induced undesirably. In order to remove the copper flakes, a wafer rework by CMP re-polish is performed. However, this re-polish will induce copper loss and degrade resistance target and uniformity. That is, resistance will become higher and uniformity will degrade because of the re-polish process. It is desired to find a method to eliminate the problems of copper flaking and metal bridging without copper loss while maintaining resistance target and uniformity.
U.S. Pat. No. 6,136,680 to Lai et al teaches a method of forming copper damascene interconnections through a fluorinated silicate glass (FSG) layer. After CMP, the wafer is annealed and subjected to a plasma treatment in order to remove Si-OH bonds and copper oxides on the surface of the FSG layer. U.S. Pat. No. 6,133,144 to Tsai et al discloses a dual damascene process. U.S. Pat. No. 6,010,962 to Liu et al describes a copper process. U.S. Pat. No. 5,759,906 to Lou shows an interconnect process.
A principal object of the present invention is to provide an effective and very manufacturable method of copper metallization in the fabrication of integrated circuit devices.
Another object of the invention is to provide a method of copper metallization wherein copper flaking and metal bridging problems are eliminated.
A further object of the invention is to provide a method of copper metallization wherein stability of the copper film is improved.
Yet another object of the invention is to provide a method of copper metallization wherein wafers with copper flake defects can be re-worked without copper loss.
Yet another object of the invention is to provide a method of copper metallization wherein copper flaking and metal bridging problems are eliminated by an annealing process.
In accordance with the objects of this invention a method of copper metallization wherein copper flaking and metal bridging problems are eliminated by an annealing process is achieved. A first metal line is provided on an insulating layer overlying a semiconductor substrate. A dielectric stop layer is deposited overlying the first metal line. A dielectric layer is deposited overlying the dielectric stop layer. An opening is etched through the dielectric layer and the dielectric stop layer to the first metal line. A barrier metal layer is deposited over the surface of the dielectric layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and barrier metal layer not within the opening are polished away wherein copper flakes form on the surface of the copper and dielectric layers after a time period. The copper layer and the dielectric layer are alloyed whereby the copper layer is stabilized and the copper flakes are removed to complete copper damascene metallization in the fabrication of an integrated circuit.